1. Field of the Invention
The present invention relates to a three-dimensional (3D) semiconductor, and more particularly, to a method of manufacturing a 3D semiconductor chip.
2. Discussion of Related Art
In recent years, semiconductor technology has been rapidly advanced. Semiconductors have been developed in smaller sizes while observing for several decades the Moore's law, stated by Gordon Moore who has been well known as the co-founder of Intel to the general public, that the number of transistors included in one chip has doubled approximately every eighteen months. Recently, semiconductor technology has been developed to manufacture semiconductors having a size of about 20 μm.
In general, semiconductor technology has been continuously developed to satisfy a demand for smaller semiconductors and the reliability of mounting semiconductors. In recent years, as there is a demand for small-sized and high-performance electric/electronic products, various semiconductor technologies employing a stacking manner have been developed.
In the semiconductor industry, the term “stacking” means stacking at least two semiconductor chips or packages in a vertical direction. When stacking is used, a semiconductor product may be manufactured to have a memory capacity that is double or more that of a semiconductor product according to the related art.
Also, stacking is advantageous in terms of an increase in a memory capacity and a mounting density and efficient use of a mounting area. Thus, research and development have been actively conducted on stacking methods.
Recently, stacking methods may be largely classified into a wafer-to-wafer (W2W) method, a die-to-wafer (D2W) method, and a die-to-Die (D2D) method.
The W2W method has a problem that a yield decreases as the number of stacked layers increases. The D2D method has a problem that only one semiconductor chip can be manufactured since stacking is performed once, but it has a high yield.